 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS AN246 Transmission lines and terminations with Philips Advanced Logic families Author: Mike Magdaluyo February 1998 Philips Semiconductors Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families Author: Mike Magdaluyo, Logic Products Group INTRODUCTION With increasing systems speeds and faster logic families, interconnect characteristics have become significant. The signal transition times of faster families can increase transmission line effects on printed circuit board traces and cables. If not taken into consideration, signal degradation can cause data errors in a system. Previous logic families with slower rise and fall times such as LS and HCMOS were not as severely affected by this issue if line lengths were not too long. For example, an HCMOS buffer with a 5 ns edge will start exhibiting transmission line effects when a circuit board trace is longer than a foot. However, with newer families, even relatively short trace lengths become very important. This application note will briefly review transmission line concepts and evaluate transmission line effects with Philips 5 volt and 3 volt BiCMOS and CMOS logic families such as ABT, AC(T), ALVC, LVC, LVT, and ALVT. For more detailed information on transmission lines, there are many other resources to refer to. The terms line or transmission line will refer to a cable or printed circuit trace medium and will be regarded as equivalent for electrical purposes, though their construction varies in real applications. AN246 Table 1. Maximum trace length in inches with 15pF loading Family HC AHC AC ALS FAST ABT LVT ALVT LVC LV ALVC tr ns 2.9 2.1 1.2 2.7 4.0 0.9 0.8 0.8 1.8 2.9 1.2 tf ns 2.9 1.6 1.7 1.7 1.4 1.2 0.6 0.7 1.8 2.9 1.1 100 18.1 10.0 7.5 10.6 8.8 5.6 3.8 4.4 11.3 18.1 6.9 70 12.7 7.0 5.3 7.4 6.1 3.9 2.6 3.1 7.9 12.7 4.8 50 9.1 5.0 3.8 5.3 4.4 2.8 1.9 2.2 5.6 9.1 3.4 35 6.3 3.5 2.6 3.7 3.1 2.0 1.3 1.5 3.9 6.3 2.4 25 4.5 2.5 1.9 2.7 2.2 1.4 0.9 1.1 2.8 4.5 1.7 As you can see, using faster edge families even with relatively short traces still requires consideration of transmission line effects. CRITICAL LINE LENGTH An interconnect is considered electrically long when the round trip propagation delay of the interconnect from the driver to the load is equal to or greater than the transition time of the driver's rise or fall time. At this point, transmission line effects become significant. Using 160ps per inch as a nominal propagation delay for 50 stripline medium and a nominal 0.9 ns rise time for a lightly loaded ABT driver with 15 pF loading, the critical line length is Eq. 1 Critical line length + 2 +2 t pd tr 160 ps in. 0.9 ns CHARACTERISTIC LINE IMPEDANCE AND CAPACITIVE LOADING A transmission line has distributed series inductance and distributed capacitance throughout its length, and can be modeled as shown in Figure 1. The line has characteristic inductance and capacitance per unit length, l, where LO is in Henries per inch, and CO is in farads per inch. L0 L0 L0 C0 l l C0 l C0 + 2.8 in. For this example, traces shorter than this can be treated as lumped elements. Traces equal to or longer than this length should be modeled as distributed elements. Table 1 shows critical line lengths at various line impedances for different Philips' logic families. Assumptions are light loading of 15 pF and a nominal 8 nH per inch characteristic inductance for a PC board trace. Formulas to determine line impedance are shown in the following section. SH00094 Figure 1. Circuit equivalent for a transmission line 1998 Feb 05 2 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 Typical characteristic impedances on PC boards can be from 50 to 100 . The impedance can be determined by Eq. 2 ZO + LO CO Likewise, the new line propagation delay will be Eq. 5 TO + TO 1) C LU CO 1) 5 pF in. 2.2 pF in. where L0 and C0 are the characteristic inductance and capacitance per unit length of the trace. The line propagation delay can be determined by Eq. 3 T O + L OC O Distributed capacitive loads lower the effective impedance of a transmission line and increase the line propagation delay. Consider a bus structure with equally spaced loads of the same value as in Figure 2. The capacitors represent the input capacitance of each receiver. + 142 ps in. + 257 ps in. Since the effective line impedance can be reduced with more loading, a driver with sufficient source and sink capability should be chosen to drive that particular impedance. This is discussed in the next section. INCIDENT WAVE SWITCHING AND DRIVER I-V CHARACTERISTICS When launching a pulse down the line, the driver needs sufficient current to change the voltage on the line. For TTL level input receivers, the guaranteed VIH and VIL levels are 2.0 V and 0.8 V. This means that the leading edge incident wave launched down the line should meet those levels to switch all receivers on the line and switch them only once. The drive current required is Eq. 6 I AV at V OH + V IH min * V OL typ ZO ABT244 L = 10 in. ZO LO CO TO C's = 65 = 9.2 nH/in. = 2.2 pF/in. = 142 ps/in. = 5 pF SH00115 Eq. 7 I AV at V OL + V OH typ * V IL max ZO Figure 2. Equally spaced capacitive loads If the driver's rise or fall time is longer than the electrical length of the spacing between the loads, the effects of individual capacitors distribute evenly across the waveform edge. This adds capacitance to the line's characteristic capacitance. The board interconnect at the receiver pin has capacitance also: via, connector, etc., and the values are added to the receiver's capacitance to form a lumped value. Suppose the interconnect capacitance is 5 pF, then the lumped distributed capacitance is 10 pF per every 2 inches or 5 pF per inch. The new line impedance, ZO', can be calculated and will be Eq. 4 ZO + ZO 1) + C LU C O As an example of incident wave switching capability, refer back to the bus structure in Figure 2. The effective line impedance is 34 . Using Equations 6 and 7, the drive current required to switch the line is determined as follows: I AV at V OH + V IH min * V OL typ ZO + 2 V * 0.2 V 36 W + 50 mA and I AV at V OL + V OH typ * V IL max ZO 65 W 5 pF in. 1) 2.2 pF in. + 3.4 V * 0.8 V 36 W + 72 mA ABT products are rated for +32 mA source current at 2 V and -64 mA sink current at 0.55 V. By referring to I-V curves you can determine if the dynamic drive current is enough to switch the line on the incident wave. From the following curves in Figures 3 and 4, note that the -76 mA at 2 V and +167 mA at 0.8 V satisfies the requirements in the above formulas. To compare the drive strength of other product families, Figures 5 through 9 show IOL and IOH currents for a typical `244 driver for the ABT16, ALVC, ALVT, LVC, LVT, and LVT16 families. + 36 W where CLU = load capacitance per unit length, pF/in. 1998 Feb 05 3 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 SH00096 Figure 3. ABT244 I-V curves SH00097 Figure 4. ABT16244 I-V curves 1998 Feb 05 4 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 SH00098 Figure 5. ALVC16244 I-V curves SH00099 Figure 6. ALVT16244 I-V curves 1998 Feb 05 5 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 SH00100 Figure 7. LVC244 I-V curves SH00101 Figure 8. LVT244 I-V curves 1998 Feb 05 6 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 SH00102 Figure 9. LVT16244 I-V curves Based on the I-V curves, all families have good drive current in the logic high state, and ABT(16), ALVT, and LVT(16) BiCMOS families have considerably stronger drive than the other families in the logic low state. The BiCMOS families have been optimized to drive backplanes. The other CMOS families are suitable for local buses and driving point-to-point loads. The following table shows recommended minimum line impedances that can be driven by the buffer/drivers of various Philips logic families: REFLECTIONS FROM IMPEDANCE MISMATCHES Since a driver has non-zero output impedance, its impedance along with the line impedance form a voltage divider. The incident wave launched down the line is a portion of the driver's voltage. When the wave encounters an impedance change from either the line or a receiver input, a portion of the wave is reflected back towards the driver (Vreflected) which is determined by the reflection coefficient r. The reflected portion is also added to the incident wave which continues propagating down the line (Vtransmitted). The relationship of these voltages are shown in the following equations: Eq. 8 o+ Eq. 9 V reflected + V incident Eq. 10 V transmitted + V incident ) V reflected Since driver and line impedances are usually mismatched, a reflection occurs at the driver and travels back towards the load. The reflection coefficient at the driver is determined by Equation 11: Eq. 11 o+ (Z driver * Z O) (Z driver ) Z O) o (Z load * Z O) (Z load ) Z O) Table 2. Minimum line impedance for logic families Logic Family ABT(16) AC/ACT ALS(-1) FAST LVT(16) ALVT LVC(16) ALVC Minimum ZO 35 50 65 50 35 35 50 50 This volley of wave reflections continues, with reflections getting smaller as the signal waveform settles. During the reflection period, the waveform may have a stairstep response--in the case of a driver's impedance higher than the line's--or it may have a "ringy" response--in the case of a driver's impedance lower than the line's. To predict the signal integrity of a waveform you can use reflection charts or Bergeron plots, but they can be cumbersome. 1998 Feb 05 7 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 Another tool that is useful for evaluating these effects is SPICE models. Philips Semiconductors offers free models for our FAST, ALS, HCMOS, ABT, ABT16, ALVC, ALVT, LV, LVC, LVT, and LVT16 product families to aid in signal integrity evaluation. The models help reduce design time by eliminating time consuming efforts of reflection and Bergeron diagrams, and they also help predict signal integrity prior to board layout. As an example, the circuit in Figure 10 was modeled and the results are shown in Figure 11. A pulse was fed into the ALVC16244 and the input and output waveforms were observed. This example illustrates the effect of reflections due to the mismatch of the driver impedance (around 10 ) and the transmission line. Note that the overshoot and undershoot in Figure 11 may not be acceptable to drive other 3V device inputs or DRAM's. To reduce the overshoot and undershoot, line termination will be necessary. ZO = 50 A ALVC16244 Driver B ALVC16374 Receiver SH00116 Figure 10. ALVC16244 driving ALVC16374 receiver SH00104 Figure 11. SPICE simulation for the circuit in Figure 10. 1998 Feb 05 8 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 TERMINATION CONSIDERATIONS AND TECHNIQUES As shown earlier, impedance mismatches between the source, line and load can cause reflections. These reflection can cause signal delays, such as the case of a stairstep type of response which requires additional line delays to reach sufficient switching threshold levels, mis-clocking from non-monotonic edges, or excess voltage/current on inputs. A signal should be terminated if it won't settle on time, if it produces overshoot or undershoot that violates the receivers input voltage or current ratings, or if it drives edge-sensitive asynchronous inputs and has non-monotonic edges. Several termination schemes can be used depending on drive current capability, power dissipation requirements, and incident wave switching requirements. There are two basic approaches to line termination: source termination and end termination. Both schemes will result in a stable signal at the far end of the line after one line delay. Source termination, however, results in a stable signal up to two line delays for loads at intermediate points on the line and at the source. More details of each scheme follows. amplitude. The wave amplitude at the first and intermediate receivers, however, are half-height and require up to one additional line delay for the reflected wave to reach the series terminator and add to the initial wave. Figure 13 shows a SPICE simulation of the reflections for this circuit and termination method. Note that the last receiver is first to switch to the full signal amplitude, while the first receiver is the last to reach full amplitude. This means that any edge-sensitive asynchronous signals should be located at the end of the line. Non-monotonic edges at the beginning and intermediate points along the line could cause false clocking of devices. Also, drivers at the beginning and at intermediate points need to be able to tolerate roughly twice the settling time. As you can see, this termination method is not very good for lines with daisy chain topologies. Source terminators work well, though, for single receiver, point-to-point loads and star type of topologies. They work well to dampen overshoot and undershoot. Source terminators dissipate no quiescent power. The AC power dissipation can be estimated by: Eq. 12 P [ f 2T DV 2R where f where T V R 2 Source Terminations Methods Figure 12 shows the configuration of a source terminated daisy chain line. Driver RS ZO' ZO' = pulse frequency = one-way line delay = VOH-VOL = termination resistance Receiver C Receiver A Receiver B SH00117 Figure 12. Source termination configuration The concept of this termination method is to try and match the loaded line impedance with the sum of the driver output and series resistor impedances. The series resistor value is equal to ZO' minus the driver impedance. The resistor should be located as close to the driver as possible. Since the sum of the driver impedance and series resistor equals the line impedance, a half-height wave travels down the line from the voltage divider effect. Assuming a reflection coefficient approaching +1 at the end of the line, the reflection adds to the half-height wave, and the voltage at the last receiver is at near full This approximation works if the pulse interval is greater than twice the line delay. For shorter pulse intervals, you can assume a worst case of DV/2 across the termination resistor at all times. With its low power dissipation, series termination is recommended for low voltage logic. As mentioned previously, the sum of source impedance and the series terminator should match the loaded line impedance. Since output impedances are different in the logic low and high states, there needs to be a compromise when choosing the termination resistance. It's probably better to slightly overdrive the line by choosing a smaller resistor to ensure fast enough edge transitions to a valid logic level. Typical values in applications range from 22 to 33 . Philips offers ABT, ALVC, ALVT, LVC, and LVT parts with built-in series terminators that have equivalent output impedances of 30 . These parts save board space by eliminating the need for a terminating resistor. Part types are designated by a "2" prefix before the part type number, e.g., 74ABT2245. 1998 Feb 05 9 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 SH00106 Figure 13. Reflections from source termination Other Series Termination Schemes Figure 14 shows a series termination used with a star stub topology. Receiver A Receiver B Stub electrical lengths should be very short, about 10% of the signal edge, to prevent reflections. This method is useful for terminating clocks and other asynchronous signals if stubs are of equal length/delay. Terminating methods for some alternative star routing is shown in Figure 15. Driver RS ZO RS = ZO - Rdriver Receiver C Receiver D SH00118 Figure 14. Series termination with star stub routing RS = ZO/3 - RD ZO Driver RD RS ZO Driver RD RS ZO RS ZO ZO RS ZO 1998 Feb 05 Equal delay branches 10 Unequal delay branches Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 Figure 16 shows another method of series termination. To reduce the drive requirements and power dissipation for this configuration, a more practical parallel Thevenin termination is shown in Figure 18 can be used. VCC R1 || R2 = ZO' ZO R1 Driver ZO RS RS RS RS R2 Receiver C ZO ZO ZO Receiver A Receiver B SH00120 SH00122 Figure 16. Series stub termination Note that the drivers at the end will be driving RS + ZO. Drivers in the middle should be strong enough to drive RS + ZO/2. Again, keep stub lengths short. Figure 18. Daisy chain topology with split resistor Thevenin termination This method is suitable for ABT, LVT, and ALVT families but not recommended for low voltage CMOS logic if power dissipation is a concern. The termination is placed at the end of the line as close to the receiver as possible. If this termination technique is used on LVC and ALVC drivers, take precaution not to connect the pull-up resistor to a 5 volt supply in a mixed 3 volt/5 volt system. This can cause 5 volt supply current to flow to the 3 volt supply through the upper PMOS transistor's parasitic diode of the driver output during the active high state. If used on a 3-State bus, avoid biasing the receiver input at its threshold switching voltage which is about 1.5 V for BiCMOS and CMOS TTL level inputs. Inputs left floating around the threshold region can consume excessive current or cause oscillations. You can use the following formula to determine values for R1 and R2 if they are not equal: Eq. 13 R1 + ZO V CC V CC and R 2 + Z O VT V CC * V T End Terminations End terminated line are recommended for distributed loads, and several methods can be used such as parallel, AC, and diode clamp methods. Figure 17 shows two parallel termination schemes. VCC ZO RT = ZO ZO RT = ZO SH00121 Figure 17. Parallel terminations With this method, the termination resistance is matched to the effective line impedance. The advantage is that this method allows for incident wave switching. The disadvantages are that you need an extremely strong driver and it consumes high static power. where VT = termination voltage. A good termination voltage to choose is 2.5 V for TTL thresholds. Assuming a 50% duty cycle, the average power dissipation of the resistors will be: Eq. 14 P + 0.5 V OH ) V OL (V - V OH) 2 ) (V CC - V OL) 2 ) CC 2R 2 2R 1 2 2 Another method to reduce quiescent power dissipation is AC termination shown in Figure 19. This method is recommended for distributed loads or when static power consumption is a concern. Driver ZO R 1 = ZO R1 C1 SH00125 Figure 19. AC termination 1998 Feb 05 11 Philips Semiconductors Application Note Transmission lines and terminations with Philips Logic families AN246 No DC current flows during quiescent high or low logic levels, but an AC current path is available through C1 to terminate the line. Choose XC to be a small percentage of ZO at the operating frequency of: Eq. 15 f+ 1 2T r where Tr is the faster of the rise or fall time Also, for DC balanced signals with 50% duty cycle, choose C such that ZOC is much greater than the pulse period. For DC imbalanced signals, choose C such that ZOC is much greater than the rise time but much smaller than half the pulse period. Provided that the duty cycle is 50%, the average voltage across C1 is midway between the driver high and low output levels. R1 will also have half the voltage swing always across it. The power dissipation across R1 will be: Eq. 16 V OH - P+ + V The same principles should be applied to this method as in the Thevenin termination. Note that drivers will need to be strong, such as the BiCMOS devices, since they will have to drive half the value of ZO. The last method of end termination discussed in this paper is diode clamp termination shown in Figure 21: VCC Driver ZO SH00123 Figure 21. Diode clamp termination The advantages are that it dissipates no power and it adds no delay to the net. The method is good to clamp overshoot and undershoot provided that it is fast enough to react to the rising or falling edge. The disadvantage is that it won't limit overshoot on 5 volt TTL drivers such as ABT. Also, it can't guarantee monotonicity on weak drivers. 2 OL 2 ZO (V OH - V OL) 2 4Z O Another method of end termination is shown in Figure 20. CONCLUSION Philips Semiconductors offers various advanced CMOS and BiCMOS families for high speed bus applications. This paper discussed aspects of transmission line effects with these families. Critical line length, line impedance, loading, and drive capability of different product families was examined. Impedance mismatches and reflections were discussed along with various termination solutions. Considerations of these various factors will help solve signal integrity issues in a design, and these factors need to be considered with their tradeoffs to satisfy the system design needs. To help make design efforts easier, Philips Semiconductors offers free SPICE models for our 3V and 5V product families to aid in signal integrity evaluation. The models help reduce design time by eliminating time consuming efforts of reflection and Bergeron diagrams, and they also help predict signal integrity prior to board layout. VCC R1 R2 VCC R1 R2 ZO ZO R1 || R2 = ZO' ZO SH00124 Figure 20. Party bus dual termination ACKNOWLEDGEMENTS Thanks to Tinus van de Wouw and Jeff West for their help and data. REFERENCES 1. Drs. Howard Johnson and Martin Graham, High-Speed Digital Design. Englewood Cliffs: PTR Prentice Hall, 1993. 2. James Buchanan, Signal and Power Integrity in Digital Systems: TTL, CMOS, and BiCMOS. New York: McGraw-Hill, 1996. 3. Steve Kaufer, Termination Improves Board Signal Quality. Electronic Engineering Times: September 2, 1996, p. 44, p. 74. 4. High Performance ECL Data Book: Design Guide Section, System Interconnect. Motorola, Inc.: 1993. 1998 Feb 05 12 Philips Semiconductors Application Note Transmission lines and terminations with Philips Advanced Logic families AN246 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03811 Philips Semiconductors yyyy mmm dd 13 |
Price & Availability of AN246
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |